GE Fanuc / ICS ICS-1555A-005 4-Channel, 160/180 MHz 16-bit ADC PMC Module with Virtex-5 SX95T User Programmable FPGA

The GE Fanuc / ICS ICS-1555A-005 is a 4-channel, 16-bit analog-to-digital converter (ADC) PMC module built around a user-programmable Xilinx Virtex-5 SX95T FPGA. It delivers simultaneous sampling at 160 MHz or 180 MHz per channel with AC-coupled 50 Ω inputs spanning 2 MHz to 300 MHz (-3 dB). The module integrates four Graychip GC4016 digital down-converters for flexible multi-band signal extraction and narrows signals to 10 MHz (-1 dB) per channel. Its PCI-X interface supports 64-bit/133 MHz master/target operation with burst-mode DMA, while 64 user I/Os connect directly to the FPGA via the Pn4 connector. Signal integrity is maintained with S/(N+D) ratios exceeding 73 dBFs at 160 MSPS and 70 dBFs at 180 MSPS, plus spurious-free dynamic range of 84 dBc at 70 MHz. Extended temperature variants are available.

Technical Specifications Analog Inputs

4 channels, AC-coupled, 50 Ω input impedance

Full-scale voltage: 1.48 dBm (0.75 Vpp) or 5 dBm (1.125 Vpp), software selectable

Input bandwidth: 2 MHz to 300 MHz (-3 dB)

Sample rate: 160 MHz or 180 MHz per channel; minimum 1 MHz

Resolution: 16-bits Sampling Clock

Internal: 100 MHz (Silicon Labs Si571)

External: 32 MHz to 180 MHz, LVTTL/sinewave compatible

External trigger: LVTTL/LVCMOS with 5V tolerance, edge-selectable

External sync: LVTTL/sinewave, -3 dB min. to +6 dBm max. Digital Down-Converters

4× Graychip GC4016 devices

Simultaneous down-conversion of up to 16 arbitrary signal bands

Configuration: up to 16 narrowband, 8 split-I/Q, or 4 wideband channels

Maximum output bandwidth: 10 MHz (-1 dB) per channel

Arbitrary center frequency tuning within passband FPGA

Xilinx Virtex-5 SX95T, user-programmable

36-Kbit block RAM/FIFOs, 25×18 DSP slices, SelectIO technology

ChipSync interface blocks, system monitor, enhanced clock management with DCMs and PLLs Interfaces

PCI-X: 64-bit/133 MHz, master/target, burst-mode DMA capable (PCI Local Bus Specification Revision 3.0, CMC/PMC P1386.1)

User I/O: 64 lines via Pn4 connector (LVDS or LVTTL) Performance

S/(N+D): >73 dBFs @ 70 MHz input, 160 MSPS; >70 dBFs @ 90 MHz input, 180 MSPS

SFDR: 84 dBc @ 70 MHz input

Key Features

Multi-band signal extraction with four integrated digital down-converters

Programmable FPGA for custom signal processing and control

Flexible sampling clock (internal or external, 32–180 MHz)

High dynamic range and low spurious content

Typical Applications

Communications signal analysis

Radar data acquisition

Test and measurement

Compatibility & Integration PCI-X master/target interface with DMA capability integrates into standard CompactPCI and PMC carrier systems. Pn4 connector provides direct FPGA access for custom I/O protocols and signal routing.