Curtiss-Wright / VMETRO Ultraview TIMBAT-PB Piggyback Module

The Curtiss-Wright / VMETRO Ultraview TIMBAT-PB is a piggyback module that extends VMEbus analyzer capabilities by integrating VME Bus Anomaly Trigger (VBAT) functionality with a dedicated timing analyzer. Designed for aerospace and defense applications, this module screens VMEbus traffic for specification violations using rule-based parallel trigger elements. It detects timing anomalies such as address signal instability during assertion and simultaneous multi-master access grants, routing violations directly to the trace memory and trigger circuitry of associated VBT-325 series analyzers.

Technical Specifications

VMEbus signals sampled: 101

External inputs: 4

Trigger output: 1

Trigger sequencer levels: 16

Built-in voltage monitor

Key Features

Rule-based parallel triggering continuously monitors VMEbus traffic for timing violations

VBAT integration screens address stability and bus master contention scenarios

External I/O connectivity via BNC connectors supports integration with auxiliary test equipment

Trigger outputs synchronize trace capture with detected anomalies

16-level sequencer enables multi-stage triggering logic

Typical Applications

VMEbus system validation and debugging in aerospace platforms

Defense electronics diagnostics requiring real-time anomaly detection

Timing violation analysis across mixed VMEbus architectures

Protocol compliance verification during system integration

Compatibility & Integration The TIMBAT-PB operates as a piggyback module attached to compatible Curtiss-Wright carrier boards, including the VPC-MkII. Integration with VMEbus analyzers - specifically the VBT-325 series (VBT-325B and VBT-325C) - provides trigger and memory management. The module pairs with other piggyback components such as S/TIM200-PB and VDRIVE-PB within broader VMEbus test systems.