Curtiss-Wright / VMETRO VBT-321B VME Analyzer Module

The Curtiss-Wright/VMETRO VBT-321B is a single-slot VME analyzer module that captures, monitors, and analyzes data traffic on VMEbus systems in real time. It detects errors, measures performance, and aids in debugging and optimizing VME-based embedded systems through comprehensive bus analysis and protocol validation.

Technical Specifications Form Factor: Single-slot VME module Trace Buffer: 2M Sample Trace Buffer @ 256-bits Slave Memory: 8 MB, locatable anywhere in VME address map; supports single cycles or block transfers up to 320 MB/s Counters: 3 × 32-bit Occurrence/Delay Counters Sequencer: 16 levels with If, Else, Elsif, Goto, Count, Delay, Trigger, Store, and Halt capabilities Interfaces: Host and Terminal connectors (Female DB-25 each), External Input (BNC), Trigger Output (BNC), 10/100 Mbit/s Ethernet, USB for PC control Front Panel: Manual Reset Switch

Key Features

Captures and analyzes VME, VME64, 2eVME, and 2eSST bus traffic including arbitration, interrupts, block cycles, and RMW operations

Multi-level Trace Viewer enables different data visualization perspectives

Optional protocol checker (-VP option) detects up to 60 VME errors automatically with background operation capability

Edge triggering and Address/Data range triggering: 8 A64 address ranges, 8 D64 data ranges

LVTTL level trigger output with programmable polarity, level, or pulse; may pulse on each stored sample

Supports normal and block cycles on any BR level with selectable RWD, ROR, ROC, or RNE release options

Compatible with piggyback modules such as VBAT-PB (VME Bus Anomaly Trigger) for enhanced protocol violation analysis

Typical Applications Debugging and performance optimization of VME-based embedded systems; real-time bus monitoring; protocol validation and error detection in complex VME architectures.

Compatibility & Integration Controlled via Windows PC with Graphical User Interface such as Curtiss-Wright's BusView™. Operates across all standard VME bus variants. Supports master and slave operations with flexible address mapping and high-speed block transfer capability.