Curtiss-Wright / VMETRO VBT-325C VMEbus Analyzer

The Curtiss-Wright/VMETRO VBT-325C is a dual-analyzer VMEbus instrument designed for protocol-sensitive capture, monitoring, and analysis of VMEbus systems and configurable P2 bus protocols. It has simultaneous independent analysis of VMEbus and secondary bus activity - including VSB, SCSI, or user-defined protocols - diagnose complex multi-bus interactions within a single acquisition window. The instrument captures all VMEbus transactions including arbitration, interrupts, block transfers, and read-modify-write cycles with protocol-aware sampling that derives timing from bus cycles themselves.

Technical Specifications Dual Analyzer Architecture

VMEbus analyzer: 101 sampled signals (address, data, control, interrupt, and bus arbitration lines)

P2 analyzer: 64 configurable signals for VSB, SCSI, or user-defined protocols

Protocol-sensitive sampling: derives clocks from bus cycles for accurate transaction tracing Timing and Analysis Depth

State analysis: up to 25 MHz

Timing analysis: up to 50 MHz (200 MHz optional with TIM200-PB piggyback)

Trace buffer: 32K samples standard (expandable to 1M samples with XMEM325-PB piggyback)

VME partition: 32K × 128 bits

P2 partition: 32K × 64 bits Triggering and Sequencing

Four full-width word recognizers per bus with address and data range capability

Trigger sensitivity: 20 ns (5 ns optional)

16-level sequencer with conditional logic (If, Else, Elsif, Goto, Count, Delay, Trigger, Store, Sampling mode, Halt)

Four 20-bit occurrence counters per bus for sequencer control

Three 20-bit delay counters per bus: 40 ns to 0.33 s range

Four 20-bit event counters per bus for statistical analysis

NOT operator on signal groups Interface and Control

PC-based operation via BusView™ GUI over RS232 connection

ASCII terminal alternative for remote operation

Key Features

Independent, simultaneous analysis of two distinct bus protocols eliminates sequential capture limitations

Protocol-aware sampling eliminates timing artifacts from external clock derivation

Flexible triggering with multi-level sequencing enables complex conditional captures

Expandable memory architecture scales trace depth for long-duration captures

Typical Applications

VMEbus system development and validation

Hardware-software integration debugging

Multi-bus protocol interaction analysis

Bus arbitration and interrupt sequence diagnostics

Compatibility & Integration Supports standard VMEbus signals and VSB, SCSI, or customer-defined P2 protocols. Optional piggyback modules extend timing analysis and trace memory capacity.