Curtiss-Wright / VMETRO / Micro Memory MM-6490D High Speed, Dual-Port 1GB VME / VME64 / RACEway Buffer Memory

The MM-6490D is a high-speed, dual-port buffer memory module for VME, VME64, and RACEway systems. This single-slot VME board delivers concurrent read/write operations through its dual-port architecture, supporting memory capacities from 128 MB to 2 GB. The module provides data transfer rates up to 160 MB/s on RACEway and 80 MB/s on VME64, with block transfer cycle times of 30 ns and 100 ns. Byte-wide parity generation and checking protect data integrity, with error status reported via CSR and BERR signals. Two independent, switch-selectable memory ports operate on 1 MB boundaries, enabling flexible configuration. The MM-6490D supports 32-bit addressing across both VMEbus and RACEway interfaces, with data widths ranging from 8 to 64 bits on VMEbus (UAT) and 32-bit multiplexed operation on RACEway. Sequential block transfers reach 256 bytes on VME and 2 KB on VME64/RACEway.

Technical Specifications

Memory Capacity: 128 MB, 256 MB, 512 MB, 1 GB, 2 GB configurations

Data Transfer Rates: RACEway up to 160 MB/s; VME64 bus 80 MB/s

Block Transfer (BLT) Cycle/Access Times: 100 ns / 30 ns (write and read)

Addressing: 32-bit for VMEbus and RACEway

Data Width: VMEbus 8, 16, 32, 64 bits (UAT); RACEway 32-bit multiplexed

Sequential Access: VME 256 bytes (BLT); VME64/RACEway 2 KB (MBLT/burst)

Control Status Register: 8-bit read/write, jumper-selectable in A16 space

Operating Temperature: 0 to +60°C

Relative Humidity: Up to 95% without condensation

Key Features

Dual-port architecture for simultaneous read and write operations

Byte-wide parity generation and checking with diagnostic write-wrong parity mode

Parity error reporting via CSR and BERR signal

Read, write, read-modify-write, and refresh operation modes

Burn-in and 48-hour memory diagnostics with 0–60°C temperature cycling

Compatibility & Integration

VMEbus Rev D (ANSI/VITA 1-1994) with VME64 support

RACEway Rev 1.4 (ANSI VITA 5-1994)

Broad integration into existing VME and RACEway infrastructure