Astronics / EADS / Talon Instruments SR101 Timing Set Module

The SR101 Timing Set Module is a precision timing generator engineered for the SR192 Digital Test Module system. It orchestrates I/O module stimulus/response operations and bus emulation by generating accurate timing signals and memory address/control signals. Each SR101 controls up to six I/O modules and operates at timing rates to 50 MHz with data rates to 25 MHz (50 MHz multiplexed). The module installs directly in the SR192 motherboard - a 2-slot "C" size VXI module - and supports one or two SR101 modules per motherboard.

Technical Specifications

Timing Rates: Up to 50 MHz

Data Rates: 25 MHz standard; 50 MHz multiplexed option

Memory Architecture: 5-memory design (Stimulus, Tristate, Record, Expect, Mask)

Memory Depth: 128K bits per channel; 256K bits multiplexed

Test Sequence Memory: 128K

I/O Module Control Capacity: Up to 6 modules per SR101

Logic Standard: TTL voltage levels

Source/Sink Capability: 50 mA

Clock Resolution: DC to 50 MHz (TS CLOCK signal determines minimum cell resolution)

Clock Source: Internal or external; SR210 Accessory Module provides programmable source (100 Hz to 50 MHz)

Key Features

Dual timing module support per SR192 motherboard for enhanced sequencing capability

Advanced sequencing via SR192 Development Environment software

Control signal generation to Unit Under Test with UUT signal testing capability

TTL-level I/O with 50 mA source/sink per channel

Compatible with SR115 bi-directional 16-channel I/O modules

Typical Applications

Digital stimulus/response testing

Bus emulation and protocol validation

Synchronized multi-module test sequences

High-speed logic signal generation and capture

Compatibility & Integration The SR101 integrates into VXI bus architecture via the SR192 motherboard, which accommodates up to 12 I/O modules, two timing modules, and one D/A module per chassis. The SR210 Accessory Module supplies programmable clock sources ranging from 100 Hz to 50 MHz for both internal timing and external device synchronization.